External Project

Last updated on Nov 27, 2022
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Yuan Jiang
Yuan Jiang
Digital IC Engineer

I’m a digital IC design engineer with a strong focus on ASIC, CPU architecture, RTL, and SoC. My experience spans RISC-V SoC tape-out on TSMC 65nm (Apple Inc. sponsored), a 3-way Out-of-Order (OoO) R10K processor, and RTL implementation of FIR filters and CNN accelerators. I’ve also worked on VLIW-based TPU core design during my 2025 summer internship at Zhonghao Xinying Technology Co., Ltd. (Taize Semiconductor R&D Center), extending ISA and building vector/scalar functional units. Feel free to connect me! 📧 yuan0minor3@gmail.com | yj2848@columbia.edu .