Publications

Yuan Jiang (2025). 4-Stage RISC-V Processor SoC Design & Tape-Out (Apple Inc. Sponsored).

Website

Yuan Jiang (2025). 3-way Superscalar R10K Out-of-Order (OoO) RISC-V Processor Design.

Github Final Report Slides

Yuan Jiang (2024). 64-Tap 16-bit Dual-Clock Fixed-to-Floating-Point FIR Filter Design Based on IBM 130nm CMOS Technology.

Github Final Report Slides

Yuan Jiang (2024). 8-bit Microprocessor Design Based on TSMC 65nm CMOS Technology.

Final Report Reference

Yuan Jiang (2023). Capstone Project: Coupled LC Oscillator Based Ising Machine. ECE Senior Design.

Poster Slides Final Report

Yuan Jiang (2023). Developing a Test System for Specific Coupled Ring Oscillator Ising Solver Chips. Chris Kim VLSI Research Group.

Poster Slides Video Final Report

Yuan Jiang (2022). Spin Filtering in DNA-like Materials. Tony Low Lab.

Slides Video Program Proposal Final Report