Developing a Test System for Specific Coupled Ring Oscillator Ising Solver Chips

Abstract

Today’s von Neumann computers struggle to deliver the speed and energy efficiency needed in solving large-scale combinatorial optimization problems, such as MAX-CUT and the Traveling Salesman. The research lab of Professor Kim has been developing a 48-node all-to-all connected coupled ring oscillator Ising solver chip that is a quantum-inspired solver, and attempts to solve these problems much more efficiently and economically. This research project will develop a chip test system to evaluate the efficiency of Coupled Oscillator-Based Ising Solver(COBI) chips in solving complex optimization problems. For Hardware, customized Printed Circuit Boards (PCB) will be designed using Altium Designer, enabling precise electrical connections and circuit continuity for distinct COBI chips. Besides, An advanced hardware platform will be established with an AMD/Xilinx Kintex-7 FPGA board and an FMC+ slot to facilitate data exchange among COBI chips. For software, a test program will be created, employing Verilog/HDL and C programming, to assess the accuracy of the COBI-generated solutions by analyzing Hamming distances among results from different datasets.

Quantum

Research Group

Professor Chris Kim’s VLSI research group.

Poster Link

oposter

Example - COBIHAM_FMC (QFN-36)

PCB layout:

COBIHAM_FMC_layout
Top side of the chip:
chip_top
Bottom side of the chip:
chip_bottom

Example - COBIRISCV2_FMC (QFN-48)

PCB layout:

COBIRISCV2_FMC_layout

Example - COBIGRADIENT_FMC (QFN-36)

PCB layout:

COBIGRADIENT_FMC_layout

Hamming Distance Analysis (HD_tests) HD_report, Source_code

kim126rp (Shil 4) example:

HD

Please find more details in Poster, Final Report, Slides and Video.

Yuan Jiang
Yuan Jiang
Digital IC Engineer

I’m a digital IC design engineer with a strong focus on ASIC, CPU architecture, RTL, and SoC. My experience spans RISC-V SoC tape-out on TSMC 65nm (Apple Inc. sponsored), a 3-way Out-of-Order (OoO) R10K processor, and RTL implementation of FIR filters and CNN accelerators. I’ve also worked on VLIW-based TPU core design during my 2025 summer internship at Zhonghao Xinying Technology Co., Ltd. (Taize Semiconductor R&D Center), extending ISA and building vector/scalar functional units. Feel free to connect me! 📧 yuan0minor3@gmail.com | yj2848@columbia.edu .